Reference
Industry Standards Crosswalk
The certifications that actually count in aerospace electronics, what each governs, and where this course covers it. These are the credentials an employer recognizes — knowing how your study maps to them is half of looking like a professional. This course is ramp-up and reinforcement for IPC certification classes — not a replacement for them.
IPC-A-610
The visual-inspection bible: what an acceptable vs. defective solder joint, placement and board condition looks like. Aerospace works to Class 3 — the strictest tier.
Where this course touches it
- Module 03 §8 — solder-joint, via and laminate defect vocabulary (cold joints, ring fractures, tombstones) maps to the defect classes A-610 catalogs
- Module 06 §2 — the five-disciplined-minutes visual inspection ritual is A-610 inspection practice at the bench
- Module 10 §1 & §4 — Class 3 acceptance mindset, the 75% plated-through-hole fill rule for Class 2 AND 3, and calibrating your eye on A-610 joint imagery
- Case File 006 (reversed tantalum) — polarity and orientation acceptance checking after rework
- Drill: ICT false-call triage — separating real acceptance defects from fixture artifacts
IPC J-STD-001
How soldering must actually be done — materials, methods, cleanliness. Has a Space & Military addendum. A-610 judges the result; J-STD-001 governs the act.
Where this course touches it
- Module 10 §4 — heat discipline, joint quality criteria, flux cleanliness and wire-prep rules arrive straight from J-STD-001 territory
- Module 10 §4 — moisture-sensitive device (MSL) handling and floor-life clocks
- Module 10 §2 — ESD discipline during soldering operations
- Module 08 §4 — flux-residue leakage as an analog failure mode is the WHY behind the cleanliness requirements
IPC-7711 / 7721
The procedures for everything you do at the bench — component removal/replacement, pad & trace repair, conformal-coat removal and restoration.
Where this course touches it
- Module 04 §4 — the short-localization ladder (split, gradient, thermal; lift components LAST) is the diagnostic discipline that precedes any 7711 rework decision
- Module 06 §9 — repair, verify, document: the loop every numbered 7711/7721 procedure lives inside
- Module 10 §5 — conformal coating removal and restoration by coating type
- Module 10 §4 — repair limits and Material Review disposition when damage exceeds them
- Toolkit: Repair Traveler + Repair Case Log — the documentation trail rework procedures expect
IPC/WHMA-A-620
Acceptability of crimps, splices and harnesses — relevant wherever connectors and cabling meet the board.
Where this course touches it
- Module 03 §7 — connectors as the #1 field-failure site: bent pins, fretting, cable strain
- Module 07 §2 — differential buses (RS-485, ARINC 429, 1553) reach the board through the harnesses A-620 governs
- Case File 003 — transient entry via the connector boundary and the sacrificial parts behind it
ANSI/ESD S20.20
The framework behind wrist straps, dissipative mats, smocks and audits. ESD damage is invisible and often latent — these rules are not ceremony.
Where this course touches it
- Module 07 §5 — why ESD is a digital-board survival rule: the walking-wounded failure mode
- Module 10 §2 — the full protected-workstation discipline: tested strap, dissipative surfaces, insulator control, shielded transport
- Quiz items on the 1 MΩ strap resistor and latent damage — the program elements S20.20 audits
AS9100
Why every step is documented, every part traceable, every nonconformance formally dispositioned. The paper trail is the product.
Where this course touches it
- Module 10 §6 — traceability, controlled stock, revision control, calibrated instruments, MRB culture
- Module 09 §4 — the documented bench-to-machine verification loop
- Toolkit: Training Record + Competency Sign-Off — artifacts a shop can file as clause 7.2 competence evidence (countersigned by a supervisor)
- Case File 002 — documenting an NTF as a fixture finding instead of shrugging it off
NASA-STD-8739
Soldering and workmanship requirements for space hardware — even tighter than Class 3 in places. Applies on space programs.
Where this course touches it
- Module 10 §1 — where the space-program workmanship tier sits relative to Class 3
- Resources page — the NASA Technical Standards portal serves the 8739 series free of charge
IEEE 1149.1 (JTAG)
In-chip test infrastructure that lets ATE verify connections on BGAs and fine-pitch parts no probe can reach.
Where this course touches it
- Module 07 §2 — recognizing the test access port (TCK/TMS/TDI/TDO) on a board
- Module 09 §1 — how ICT uses boundary scan to clear unprobeable BGA joints
- Module 07 §6 — proving a processor's connections before condemning big silicon