Teradyne Machines & Automated Test (ATE)

Study an annotated diagram

Your shop's Teradyne testers are the gatekeepers: they decide what's "failed" and hand you tickets. Understanding how the machine tests tells you how to read its tickets — including when to believe them and when the machine itself is the problem. The ICT fixture diagram and guarding illustration are in visuals/03-test-equipment.html ↗.

1. The two main flavors of board test

In-Circuit Test (ICT) — "test the parts"

Teradyne's TestStation family (descended from the GenRad testers) is the classic ICT platform. The board sits on a bed-of-nails fixture: hundreds–thousands of spring-loaded probes ("pogo pins") press against test pads and vias on the board's underside (vacuum or mechanical press pulls the board down). The tester then measures each component individually:

• Shorts/opens testing: the program tests covered nets and accessible connections for unintended opens/shorts, subject to fixture access, thresholds and the test strategy. Coverage is not every net against every other net; check the program's coverage report and abort conditions.
• Analog in-circuit: measures covered components using a programmed method and available fixture access. Guarding controls selected node potentials to reduce parallel-path current. The guard voltage and residual error depend on circuit topology; not every neighboring node is simply driven to zero. Compare the tester method with a bench measurement rather than assuming they are equivalent.
• Digital/vector tests: powered, the tester drives input patterns into ICs and checks output responses against truth tables — catches dead gates, stuck pins, missing/wrong/backwards chips.
• Boundary scan (IEEE 1149.1 / JTAG): supported devices can drive and observe scan-accessible pins through the test interface. Coverage depends on the devices, board access and test program; it does not automatically verify every solder ball or internal function.
• Vectorless/capacitive opens test (e.g., FrameScan-type techniques): a sensor plate over an IC detects whether each pin is actually soldered, without powering the part — catches lifted leads on fine-pitch parts.

What ICT is great at: missing, wrong, backwards, shorted, open — assembly defects, located to the component. What it can't see: marginal timing, parametric drift under real operating conditions, anything functional.

Functional Test (FT) — "test the behavior"

The board is powered and exercised as it would be in the aircraft: real stimuli in, real responses measured, often through the edge connector only. Teradyne and in-house functional testers run these. A functional failure ticket names a failed test step and a measured behavior ("Output 3 voltage 2.31V, limits 4.75–5.25") — localizing that to a component is your job, using the test spec, the schematic, and modules 06 — Troubleshooting Methodology–08 — Analog Board Troubleshooting.

(You may also meet flying probe testers — ICT without a fixture, a few robotic probes flying point to point; slower, fixture-free, common for low volumes.)

2. Reading a failure ticket like a repair tech

A typical ICT analog failure line gives you: designator, test name, measured value, nominal, limits, and the nets/pins involved. Example:

R147  RES  Measured: 14.82k   Nominal: 10.0k   Limits: 9.0k–11.0k   FAIL

Your interpretation tree — in rough order of real-world likelihood:

1. Joint/trace open or cracked at R147 or its test pads (a high reading calls for verification of probe contact, program, part identity and connections before diagnosis)
2. Fixture problem — dirty/bent/worn pogo pin, debris on the test pad, board not seated. Especially suspect when: the same test fails on many boards suddenly, a retest passes ("re-seat and re-run" is legitimate ONCE as a fixture check, never as a repair strategy), or the failing pad looks unmarked while neighbors show witness dimples.
3. Wrong part installed (14.82k ≈ a 15k part — value-adjacent readings are a strong wrong-part hint)
4. The actual component drifted/failed

A shorts-test failure names two nets: get the schematic/CAD viewer, see where those nets run adjacent — solder bridge (check rework areas first), dendrite, cracked MLCC between them, crushed FOD.

A digital/vector failure names a device and pins: rails to the device, joints on those pins (vectorless opens result if available), then the upstream logic feeding it, then the device.

Golden rule: the ticket is a starting coordinate, not a verdict. Verify at the bench with the DMM before any iron touches the board. Boards that bounce between "fails at ICT, can't duplicate at bench" are telling you: intermittent joint (the fixture press flexes the board!) or fixture trouble. Fixture-press flex reproducing a failure is actually a gift — it tells you the fault is mechanical; go flex the board gently at the bench under continuity and watch.

3. Working with the test platform

• Learn to re-run the specific failing test, not just the whole program — fast iteration while diagnosing.
• Use the datalog/history: the same unit's previous results, and the failure Pareto across the fleet of this assembly. a frequent ticket on the assembly's Pareto is a useful starting hypothesis — ask the senior techs and the test engineers; every shop has tribal knowledge wrapped around each test program.
• Befriend the test engineers. When you find a ticket that systematically lies (bad guard, marginal limit, fixture wear), reporting it improves everyone's life. Repair techs are the feedback loop of a test floor.
• Fixture care is part of accuracy: pins wear and gunk up; if you're authorized, learn the shop's fixture-maintenance and verification routine (self-test/verification boards).
• ESD and handling rules apply at the tester too — boards ride in and out of fixtures on the same wrist-strap-and-tote discipline as the bench (10 — Aerospace Standards, ESD, and Workmanship).

4. The bench ↔ machine workflow (your daily loop)

1. Ticket arrives with the board.
2. Read full ticket + history. Pull schematic/BOM/assembly drawing.
3. Bench: visual inspection → verify the ticketed measurement manually (DMM at the actual component, both polarities, golden-board comparison if available).
4. Diagnose to root cause (06 — Troubleshooting Methodology) — component vs joint vs trace vs fixture.
5. Repair per IPC-7711/7721, document.
6. Back to the machine: re-run the failed test, then the full program (your repair must not create new failures — heat near an MLCC can crack it; a slipped probe can nick a trace).
7. Close the paperwork with cause/action/verification.

5. Vocabulary you'll hear day one

6. Self-check

1. Why can ICT measure a resistor accurately without lifting a leg, when your DMM can't? Reveal answer
2. The same test fails on five consecutive different boards this morning. First suspect? Reveal answer
3. ICT says a BGA pin is open. What technology checked it, and what's your bench reality? Reveal answer
4. A board fails at ICT, passes at your bench, repeatedly. Best hypothesis and next action? Reveal answer
5. Why re-run the FULL program after a repair, not just the failed step? Reveal answer

Next: 10 — Aerospace Standards, ESD, and Workmanship